Department of Electrical Engineering, National Taipei University of Technology find us on facebook(將另開視窗)
Search this site | set the webpage to BLUE style set the webpage to ORANGE style set the webpage to GREEN style set the webpage to PURPLE style set the webpage to GRAY style ENLARGE the webpage | Site Map | Home | 中文(Chinese)
Home > People > Faculty > Pang-Jung Liu > Timetable ::: Backgroud | Teaching Timetable | Publication
::: Pang-Jung Liu
Pang-Jung Liu photo
Teaching Timetable for Spring Semester Year 2019
Course Name Class Sun Mon Tue Wed Thu Fri Sat
Electronics

4EE2C
[電機二丙]

  8 9     5    
Design and Practice of Integrated Circuit Layout

產業接軌課程(研)
[產業接軌課程(研)]

GEE
[電機所]

          6 7 8  
Design and Practice of Integrated Circuit Layout

電子4A
[電子四甲]

電子4B
[電子四乙]

電子3A
[電子三甲]

電子3B
[電子三乙]

          6 7 8  
:::
10608台北市忠孝東路三段1號 電話:(02)27712171 #2100 傳真:(02)27317187
Copyright © 2019 國立臺北科技大學電機工程系 All Rights Reserved.
如對網頁內容有任何建議,請與我們聯絡
1783487 Visits
since May 26, 2003.